Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the semiconductor structures has provided significant improvement in the speed, performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced as the sizes of CMOS devices continue to decrease.
One such problem is seen in devices that utilize poly-oxide structures. For example, split-gate transistors, which are commonly used in memory devices, are generally formed by depositing a polysilicon layer on a wafer. A masking material, such as silicon nitride (Si3N4), is formed and patterned on the polysilicon wafer to define areas that are to become a poly-oxide and a floating gate of the split-gate transistor. The exposed portions of the polysilicon are oxidized, and the masking material is removed. The poly-oxide regions act as a mask during an etching process to remove the unwanted polysilicon. The split-gate transistor is completed by forming an inter-poly oxide layer and a control gate.
During oxidation, however, the polysilicon has a tendency to oxidize along the grain boundaries of the polysilicon. In smaller designs, particularly in designs in which sharp, straight edges are desired, the oxidation along grain boundaries results in irregular etching patterns of the unwanted polysilicon. In some cases, the oxidation along grain boundaries can cause the polysilicon to bridge between elements, thereby rendering the devices inoperative. This phenomena is increasingly troublesome as device sizes decrease.
Therefore, there is a need for semiconductor devices having poly-oxide structures with a reduced amount of oxidation along grain boundaries.